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Hazards and delay padding New download by University of Hamburg

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Description of Hazards and delay padding
Hazards and delay padding was developed as an accessible Java-based tool that manages to simulate two circuits that result in a dynamic hazard.

The top placed circuit is used to simulate the basic structure responsible for a dynamic 1-hazard (0-1-0 transition).

The second circuit uses the same structure and replaces the AND gate with and OR one. The last circuit manages to demonstrate the use of gate-delays.



Tags:   And , Circuit , Delay , Dynamic , Hazard , Hazards , padding , Simulation , Simulator

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